1. Field of the Invention
The present invention relates in general to the field of analog/digital conversion circuits or converters (ADCs), particularly to ADCs featuring high resolution and wide band.
2. Description of the Related Art
In several typologies of ADCs, multibit digital/analog converters (DACs) are used. Examples are the ADCs with the so-called pipelined architecture, the ADCs with sigma-delta architecture with multibit quantizers, and the ADCs with MASH architecture.
The use of multibit DACs within an ADC is one of the techniques for increasing the overall ADC resolution.
A disadvantage in the implementation of these ADC structures is the error introduced in the converted signal by the multibit DACs. In particular, such error derives from the inevitable mutual differences between the one-bit conversion elements composing the multibit DAC, and translates in a non-linearity of the ADC.
Considering for instance a pipelined ADC, the linearity requirements for the multibit DAC located downstream the flash ADC in the first ADC stage coincide with those for the whole converter, since the linearity error introduced by the DAC acts in the same position as the signal to be converted. Mutual differences between the one-bit conversion elements of the multibit DAC, for instance formed by switched-capacitor circuits, cause the lowering of the signal/noise and distortion ratio (SNDR) and the reduction of the spurious-free dynamic range (SFDR) of the ADC, because of the appearance of a harmonic distortion.
In order to try and obviate to the distortion problems introduced by the differences between the one-bit conversion elements of the multibit DACs, permutation or, in jargon, scrambling techniques of the input signals to the DACs have been proposed.
Thanks to these techniques, the effects of harmonic distortion are significantly reduced, and the SFDR is improved; nevertheless, the background noise raises since, because of the scrambling, the energy that would be concentrated in the harmonic components of the signal is spread over the whole signal spectrum. Such raising of the background noise is less acceptable the higher the desired resolution of the ADC.
US 2002/0041248 A1 describes a method of cancellation of the error introduced by the DAC of the first stage of a pipelined ADC. The DAC includes a digital encoder that randomly permutes the connections between the outputs of the flash ADC and the one-bit conversion elements of the DAC. A digital noise cancellation logic circuit for the cancellation of the noise the introduced by the DAC is provided; such circuit receives the random bits controlling the encoder, parity bits and the digital residue sum of the digital outputs of the stages downstream, and produces an estimation of the error introduced by the first stage. Such estimation, subtracted from the digital signal produced by the stages downstream, is calculated by performing an average over a number of samples equal to at least 225.
In such a document, the noise estimation is made possible thanks to the adoption of a well precise and rigid permutation law of the connections between the outputs of the flash ADC and the one-bit conversion elements of the DAC.
The Applicant has observed that the method of error cancellation described in such document involves a rather high circuit complexity.
The Applicant has also observed that the method of error estimation described in such a document, requiring an average over a very large number of samples, is rather slow. The time required by ADC output to converge to the corrected value is therefore rather long. For instance, if the ADC operates at a frequency of 80 MHz, the convergence time could be of the order of 1 second.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.